Payment Terms | T/T, Western Union,PayPal |
Supply Ability | 10000pcs/months |
Delivery Time | 1-3 workdays |
Packaging Details | Standard |
Packaging | Tray |
Mounting Style | SMD/SMT |
Package / Case | FBGA-180 |
Supply Voltage | 1.3095 V-1.3905 V |
Organization | 256 M x 32 |
FPQ | 1260 |
Brand Name | original |
Model Number | MT61K256M32JE-14-A |
Certification | ISO9001:2015standard |
Place of Origin | original |
View Detail Information
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Product Specification
Payment Terms | T/T, Western Union,PayPal | Supply Ability | 10000pcs/months |
Delivery Time | 1-3 workdays | Packaging Details | Standard |
Packaging | Tray | Mounting Style | SMD/SMT |
Package / Case | FBGA-180 | Supply Voltage | 1.3095 V-1.3905 V |
Organization | 256 M x 32 | FPQ | 1260 |
Brand Name | original | Model Number | MT61K256M32JE-14-A |
Certification | ISO9001:2015standard | Place of Origin | original |
High Light | MT61K256M32JE-14-A 8gb emmc flash memory ,8gb emmc flash memory 256MX32 ,dram controller IC GDDR6 8G |
MT61K256M32JE-14:A Original DRAM GDDR6 8G 256MX32 FBGA Memory Data Storage
Features
• VDD = VDDQ = 1.35V ±3%, 1.25V ±3%, and 1.20V –2%/+3%
• VPP = 1.8V –3%/+6%
• Data rate: 12 Gb/s, 14 Gb/s, 16 Gb/s
• 2 separate independent channels (x16)
• x16/x8 and 2-channel/pseudo channel (PC) mode configurations set at reset
• Single ended interfaces per channel for command/ address (CA) and data
• Differential clock input CK_t/CK_c for CA per 2 channels
• One differential clock input WCK_t/WCK_c per channel for data (DQ, DBI_n, EDC)
• Double data rate (DDR) command/address (CK)
• Quad data rate (QDR) and double data rate (DDR) data (WCK), depending on operating frequency
• 16n prefetch architecture with 256 bits per array read or write access
• 16 internal banks
• 4 bank groups for tCCDL = 3tCK and 4tCK
• Programmable READ latency
• Programmable WRITE latency
• Write data mask function via CA bus with single and double byte mask granularity
• Data bus inversion (DBI) and CA bus inversion (CABI)
• Input/output PLL
• CA bus training: CA input monitoring via DQ/ DBI_n/EDC signals
• WCK2CK clock training with phase information via EDC signals
• Data read and write training via read FIFO (depth = 6)
• Read/write data transmission integrity secured by cyclic redundancy check
• Programmable CRC READ latency
• Programmable CRC WRITE latency
• Programmable EDC hold pattern for CDR
• RDQS mode on EDC pins
DRAM | |
RoHS: | Details |
SGRAM - GDDR6 | |
SMD/SMT | |
FBGA-180 | |
32 bit | |
256 M x 32 | |
8 Gbit | |
1.75 GHz | |
1.3905 V | |
1.3095 V | |
0 C | |
+ 95 C | |
MT61K | |
Tray | |
Brand: | Original in stock |
Moisture Sensitive: | Yes |
Product Type: | DRAM |
Factory Pack Quantity: | 1260 |
Subcategory: | Memory & Data Storage |
Unit Weight: | 0.194430 oz |
Company Details
Business Type:
Trading Company
Year Established:
2004
Employee Number:
50~100
Ecer Certification:
Active Member
Founded in 2004, Walton Electronics CO.,LTD is a scaled and professional independent distributor of electronic components in Shenzhen , China. Committed to the world's leading brands of electronic components distribution integration services, mainly engaged in active components , integrated circ... Founded in 2004, Walton Electronics CO.,LTD is a scaled and professional independent distributor of electronic components in Shenzhen , China. Committed to the world's leading brands of electronic components distribution integration services, mainly engaged in active components , integrated circ...
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